The present invention relates to the field of electronic circuits, and in particular, programmable phase shift circuitry.
Many electronic systems use a master clock signal to synchronize the operation of all the circuitry and integrated circuit. A fundamental concept in electronic design, synchronous operation is important to ensure that logic operations are being performed correctly. In a system, an integrated circuit may generate its own internal clock based on the master clock signal. For example, this integrated circuit may be a microprocessor, ASIC, PLD, FPGA, or memory. The internal clock is synchronized with the master clock. And in order to ensure proper operation, it is often important to reduce skew for the internal clock of the integrated circuit.
The integrated circuit may use an on-chip clock synchronization circuit such as a phase locked loop (PLL) or delay locked loop (DLL). The synchronization circuit locks or maintains a specific phase relationship between the master clock and the internal clock. When the system is started, it is desirable that the internal clock be locked to the master clock as rapidly as possible. Under some circumstances, such as when there is a wide frequency difference between the two clock, the locking time may be slow. This is because the locking time may be dependent on the slower of the two frequencies. A slower locking time is undesirable because it will take longer for the system to initialize before normal operation. Also, as the master clock varies, it will take longer for the clock synchronization circuit to track these variations.
Therefore, techniques and circuitry are needed to address this problem of clock synchronization circuitry with slow lock acquisition times. Further, it is desirable to provide programmable phase shift selection.